With a solid-state imaging device having a known architecture, photoelectric conversion units and peripheral circuits are separately formed on different substrates which are electrically connected with each other by using a micro bump.
Japanese Patent Application Laid-Open No. 2009-170448 discusses a backside illumination solid-state imaging device including a first substrate and a second substrate stuck together. The first substrate includes pixels, photoelectric conversion units, and a reading circuit for reading signals. The second substrate includes peripheral circuits for processing signals read out from pixels.
Generally, to read signals from a solid-state imaging device at high speed, the solid-state imaging device includes a plurality of parallel processing circuits for parallelly applying similar signal processing to signals from the plurality of pixels. Exemplary parallel processing circuits include a column amplifier and a row AD unit provided for each pixel column.
A direct current (DC) voltage is supplied to such a plurality of parallel processing circuits performing similar processing, to enable them to perform a desired operation. As the DC voltage, a desired voltage is supplied via a common DC voltage supply wire to the parallel processing circuits performing similar processing. The parallel processing circuits are provided on the second substrate. It is desirable not to provide other circuits on the first substrate to provide an as large opening of the photoelectric conversion units as possible. Therefore, a number of circuit elements must be provided in an area for providing the parallel processing circuits on the second substrate, possibly reducing the degree of freedom of wiring layout. To increase the degree of freedom of wiring layout, it is necessary to provide a large area for providing the parallel processing circuits, resulting in an increase in chip area.
Therefore, allocating a large area for the above-mentioned DC voltage supply wiring is difficult, and may produce a predetermined resistance in the DC voltage supply wiring. There arises a problem that an alias is likely to occur when a resistance is produced in a wiring for supplying a DC voltage to the parallel processing circuits. In particular, the larger the chip area, the more an alias is likely to occur.